Plasma processing has become an integral part of the fabrication of integrated circuits since it offers advantages in terms of directionality, low temperature and process convenience. However, plasma processing also offers increased damage potential because of surface charging of floating gates in MOS devices. With the continued increase in gate oxide thickness to improve device performance, this type of damage is becoming more of a concern. The damage can degrade all of the electrical properties of a gate oxide, which include the fixed oxide charge density, the interface state density, the flatband voltage, the leakage current and the various breakdown related parameters.
Evidence is mounting that the primary cause of oxide damage during plasma etching is charge buildup on the conductors. Plasma nonuniformity across the wafer surface plays a major role in this damage. For example, plasma nonuniformity produces electron and ion currents that do not balance locally and can generate oxide damage. These plasma inconsistencies are caused by hardware (e.g., poor electrode design, nonuniform and/or time-varying magnetic fields) or by a poor choice of process conditions (e.g., use of highly electronegative gas, choosing flows and pressures that lead to unstable plasmas). Additional causes include transient surge currents produced by gas chemistry changes at endpoint and changes in plasma exciting power or coupling capacitor discharges. Etch rate uniformity does not necessarily correlate with plasma uniformity or oxide damage. For instance, a pure Cl.sub.2 plasma caused less damage than a plasma containing a mixture of Cl.sub.2 and SF.sub.6 even though the pure Cl.sub.2 plasma produced about twice the etch rate nonuniformity as the plasma with a Cl.sub.2 /SF.sub.6 mixture.
There are three main current components at the surface of a wafer placed in an RF plasma. While at 13.56 MHZ, the largest is the RF displacement current; this is usually of secondary importance in surface charging because of the low impedance presented by the oxide. Next, there is positive ion flux that is responsible for anisotropic etching. The flux average is nearly constant with time and depends linearly on the local plasma density. The final component, electron flux, flows briefly in every RF cycle to balance the ions lost from the central plasma region. In a uniform plasma, the ion and electron conduction currents locally balance each other over the RF conduction cycle. Charging is not a problem and the surface potential stays close to that of the substrate.
The situation for a nonuniform plasma differs significantly. Ion and electron currents do not have to balance locally through the RF cycle, although there is a net balance over the electrode as a whole. For example, the electron current can be higher than ion current where the plasma potential is at a minimum; where the potential is a maximum, the opposite is true. Also, where excess ion current occurs, the imbalance (e.g., net current flux to the wafer) causes wafer surface charging and results in increased voltage across the gate and decreased voltage across the sheath. The charge buildup continues until the currents balance or the oxide begins to conduct. This feedback mechanism is caused by the exponential dependence of electron current on sheath voltage.
The VLSI industry is focusing on solutions to process-induced plasma damage in product devices. Such damage is caused by cumulative net charge deposition on wafers during plasma processing, where unbalanced plasma charges up the gate dielectric to a level exceeding the dielectric breakdown field. Because of the charge collected by the long conductive gate polysilicon chain in VLSI devices, a seemingly low plasma charging can become multiplied by a ratio factor when discharging through the gate insulator. The ratio factor, called the antenna ratio, is the gate poly area to gate dielectric area.
For the 0.25-0.35 micrometer feature devices, the circuit poly antenna ratio can range from 5:1 to 50:1. The implication is that with a floating gate poly, the case of most in-process product devices prior to first metal, the device gate oxide can experience electrical breakdown during plasma charging more easily than one without, by five to 50 times. Because there is no breakdown current limiter, such dielectric zapping is destructive, leading to device poly to substrate leakage, and device yield is degraded. In the case where the plasma charging buildup may not yet reach the breakdown but goes beyond half the breakdown, the tunneling current is sufficient to damage the oxide-silicon electronic structure that introduces excessive interface states if not properly annealed. Devices with interface damage drift with time. Thus the device reliability is at stake.
Plasma-induced charging damage characterization using test structures requires fast-turn-around between a questionably plasma step and electrical testing to be most useful. MOS capacitor structures provide cheaper and faster fabrication than transistors and also can be pretested to insure their calibration. The C-V measurement is regarded as one of the most sensitive techniques for plasma damage in many cases. However, C-V measurements are slow, sensitive to noise and difficult to automate. Charge-to breakdown Q.sub.bd is another option, but it requires long times to breakdown at low gate currents. Accelerated Q.sub.bd measurements use larger injecting currents but lowers this measurement sensitivity. Recently, a new voltage time (V-t) method was proposed which uses low constant current stressing and measures the biased voltage change with time (dV/dt). It was found that dV/dt is related to the initial electron trapping rate (IETR), which is proportional to pre-existing damage. So far, there has been no comparison of the sensitivity of the different methods or their limitations. So, it is necessary to establish basic understanding of these issues for future industry standards of damage testing. To determine whether the device has been damaged by fabrication charge build-up, manufacturers have incorporated antenna structures into the semiconductor devices. These structures may be employed to test the device and determine whether charge damage has occurred in the device during the fabrication process.
Unfortunately, however, the antenna structure suffers from certain disadvantages. For example, the antenna structure size is typically directly proportional to its damage sensitivity. Therefore, to obtain a reading on a very small charge, a larger antenna ratio (poly/oxide areas) structure is required. In many cases, these larger antenna structures are necessary because the charge damage that often occurs in the device is very small.
Moreover, these antenna structures are unable to isolate the specific device layers that are damaged, when multi-layer chips are involved. Thus, it is not possible to determine what part of the process has caused the charge damage, and due to the complexity of fabrication of the antenna structure, time delays and corresponding overall costs involved, frequent testing during the fabrication process is typically prohibitive.
Accordingly, what is needed in the art is a cost effective way to determine process-induced damage and direct the adjustment of the appropriate process parameters on a frequent basis.